MATCH_ALL=MATCH, MM_ENA=MONITOR_MODE_DISABLE, ENA_SCL=HIGH
Monitor mode control register.
| MM_ENA | Monitor mode enable. 0 (MONITOR_MODE_DISABLE): Monitor mode disabled. 1 (THE_I2C_MODULE_WILL_): The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. |
| ENA_SCL | SCL output enable. 0 (HIGH): When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 1 (NORMAL): When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] |
| MATCH_ALL | Select interrupt register match. 0 (MATCH): When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 1 (ANYADDRESS): When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. |
| RESERVED | Reserved. The value read from reserved bits is not defined. |